Aspects of the invention relate generally to processing semiconductor wafers and more particularly to controlling and optimizing wafer nanotopography during processing.
Semiconductor wafers are commonly used as substrates in the production of integrated circuit (IC) chips. Chip manufacturers require wafers that have extremely flat and parallel surfaces to ensure that a maximum number of chips can be fabricated from each wafer. After being sliced from an ingot, wafers typically undergo grinding and polishing processes designed to improve certain surface features, such as flatness and parallelism.
Simultaneous double side grinding operates on both sides of a wafer at the same time and produces wafers with highly planarized surfaces. Grinders that perform double side grinding include, for example, those manufactured by Koyo Machine Industries Co., Ltd. These grinders use a wafer-clamping device to hold the semiconductor wafer during grinding. The clamping device typically comprises a pair of hydrostatic pads and a pair of grinding wheels. The pads and wheels are oriented in opposed relation to hold the wafer therebetween in a vertical orientation. The hydrostatic pads beneficially produce a fluid barrier between the respective pad and wafer surface for holding the wafer without the rigid pads physically contacting the wafer during grinding. This reduces damage to the wafer that may be caused by physical clamping and allows the wafer to move (rotate) tangentially relative to the pad surfaces with less friction. While this grinding process can improve flatness and/or parallelism of the ground wafer surfaces, it can cause degradation of the topology of the wafer surfaces. Specifically, misalignment of the hydrostatic pad and grinding wheel clamping planes are known to cause such degradation. Post-grinding polishing produces a highly reflective, mirrored wafer surface on the ground wafer but does not address topology degradation.
In order to identify and address topology degradation concerns, device and semiconductor material manufacturers consider the nanotopography of the wafer surfaces. For example, Semiconductor Equipment and Materials International (SEMI), a global trade association for the semiconductor industry (SEMI document 3089), defines nanotopography as the deviation of a wafer surface within a spatial wavelength of about 0.2 mm to about 20 mm. This spatial wavelength corresponds very closely to surface features on the nanometer scale for processed semiconductor wafers. Nanotopography measures elevational deviation of one surface of the wafer and does not consider thickness variations of the wafer, as with traditional flatness measurements. Two techniques, light scattering and interferometry, are generally used to measure nanotopography. These techniques use light reflected from a surface of a polished wafer to detect very small surface variations.
Although nanotopography (NT) is not measured until after final polishing, double sided grinding is one process that affects the NT of finished wafers. In particular, NT defects like C-Marks and B-Rings take form during grinding process from misalignment of the hydrostatic pad and grinding wheel clamping planes and may lead to substantial yield losses. Current techniques designed to reduce NT defects caused by misalignment of hydrostatic pad and grinding wheel clamping planes include manually re-aligning the clamping planes. Unfortunately, the dynamics of the grinding operation and the effects of differential wear on the grinding wheels cause the planes to diverge from alignment after relatively few operations. The alignment steps, which are highly time consuming when performed by an operator, must be repeated so often as to make it a commercially impractical way of controlling operation of the grinder. Additionally, current techniques do not inform the operator of the particular adjustments that should be made to the clamping planes. Instead, the operator is merely provided with data describing the surface of the wafer and then uses trial and error to find an alignment that reduces the nanotopography degradation. Accordingly, the manual alignments are inconsistent among operators and often fail to improve wafer nanotopography.
Further, there is usually some lag between the time that undesirable nanotopography features are introduced into a wafer by a double side grinder and the time they are discovered. After double side grinding, the wafer undergoes various downstream processes like edge polishing, double sided polishing, and final polishing as well as measurements for flatness and edge defects before the NT is checked by a nanomapper or the like. Thus, wafer nanotopography is not known near the time that the wafer is removed from the grinder. Instead, nanotopography is only determined by conventional processes after the ground wafer has been polished in a polishing apparatus. As such, undesirable nanotopography features introduced into the wafer by the double side grinder cannot be identified until post-polishing. Moreover, the wafer is not measured until the cassette of wafers is machined. If suboptimal settings of the grinder cause an NT defect, then, it is likely that all the wafers in the cassette will have this defect leading to larger yield loss. In addition to this unavoidable delay in conventional wafer processes, the operator must wait for each cassette to be processed before getting feedback from the measurements. This leads to a considerable amount of down-time. If the next cassette is already ground before receiving the feedback, there is a risk of even more yield loss in the next cassette due to improper grinder settings.